PETsys Time-of-Flight Data Acquisition Board

Figure 1: Picture of the DAQ board.

 

   The PETsys TOF DAQ version 2 board (Fig. 1) is the core of the data acquisition system. It is equipped with a Kintex-7 FPGA, it collects data from the FEB/D_v2 boards (Fig. 2), and transmits these data to the DAQ computer using four PCI express 2.0 bus lines. Each FEB/D collects data from up to eight Front-End Modules equipped with TOF2 ASICs [1]. Up to twelve chains of FEB/D boards can be connected to the DAQ board using high-speed HDMI serial links transmitting data at 4.8 Gbps. The maximum event transfer rate per link is 72 M events/s. The DAQ board can accept an external veto signal and will distribute this veto signal to the FEB/D boards causing these to ignore all events received from the ASICs.
The fan-out box is connected to the DAQ board with a 12-channel CXP copper cable assembly plus one HDMI (A-A) cable. Twelve HDMI serial links between the fan-out box and the FEB/D boards are used for configuring all TOF ASICs in the front-end system, for providing the system clock at 160 MHz, and for providing the synchronisation signals.
Alternatively, the DAQ board can also be used in optical data collection mode. In this mode the link between the FEB/D boards in the daisy-chain, and the link between the master FEB/D and the DAQ board, is provided by optical fibres. In this mode the fan-out box is only used for distributing clock and sync signals, and for sending veto signals.
A master FED/D board can be daisy chained with up to three slave FEB/D boards. In this way the DAQ board and the FEB/D boards together form a complete and scalable data acquisition system that can handle tens of thousands of SiPM channels. If only 12 or less FEB/D boards are required, the clock and sync signal are distributed using a single fan-out box. If more than 12 FEB/D boards are needed, several fan-out boards are arranged in a tree architecture as shown in figure 4.

 

 

Main Features

  • Single PCIe board providing data acquisition of TOF PET ASICs
  • Compatible with FEB/D boards
  • Data readout of twelve master FEB/D boards and associated daisy-chained slaves
  • Max total input event rate: 12x72 M events/s
  • Coincidence trigger implemented in the FPGA
  • Data output rate to computer 250 M events/s
  • Operation frequency 160-200 MHz
  • Readout of frontend temperature sensor
  • Readout of TOF ASIC dark counters
  • Equipped with Kintex7 FPGA