PETsys TOF FEB / D board (Readout System)
Download PETsys TOF FEB / D board (Readout System) PDFPETsys Time-of-Flight Front End Board / D
The PETsys TOF Front-End Board D version 2 (FEB/D_V2) (Fig. 1) is part of the PETsys SiPM readout system. The Readout System has three different components: the Front-End Module (Fig. 2), the FEB/D_v2 boards and the DAQ board (Fig. 3). Together these allow assembling a complete and scalable data acquisition system for several tens of thousands SiPM channels for Time Of Flight PET, or similar, applications.
The FEB/D is equipped with a Kintex 7 FPGA. It receives the data from the ASICs in the Front-End Modules, and sends the data to the DAQ board in the data acquisition computer. The FEB/D_V2 also receives configuration, clock and sync signals from the DAQ board and distributes them to the ASICs. Optionally, the DAQ board can receive an external veto signal and distribute this veto signal to the FEB/D boards. The FEB/D will ignore all events while the veto signal is on.
Each FEB/D_V2 board measures 104.5x104.5 mm2. Eight Front-End modules can be connected to one FEB/D board, using either direct board-to-board connectors or using flexible flat cables. Each FEB/D board collects the data from the Front-End Modules and transmits assembled data frames to the DAQ using an electrical HDMI serial link or using a high-speed optical link. Several FEB/D boards can be daisy-chained and interfaced to a single DAQ board input. The maximum event rate of the output link (HDMI or optical) is 72 M events/s.
A mezzanine on the The FEB/D_V2 (middle mezzanine on figure 1) supplies bias voltages to the SiPMs. The default mezzanine provides 64 positive bias voltages in the range 5-100 V, with a maximum current of 550 μA per bias line. A customised mezzanine version, e. g. supplying negative bias voltage, or a larger current, can be developed on request.
DC-DC converters and regulators on the FEB/D motherboard provide the low voltages for the ASICs.
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Figure 1: FEB/D_V2 board . |
Main Features
- Reading up to 2048 independent SiPM channels from.
- Equipped with Kintex 7 FPGA.
- Compatible with Front-End Modules with 128 or 256 channels
- Data output mezzanine: micro HDMI, and optical
- Max event output rate (HDMI links or optical): 72 M events/s
- Daisy chaining of data output data links allows reading up to 48 FEB/D boards with one DAQ board.
- External clock and synchronization provided by the HDMI cable.
- Clock frequency 160-200 MHz.
- External supply voltage: 12 Vdc.
- On board DC-DC converters supply power to the ASICs in the FEB/A boards.
- SiPM bias voltages produced in a mezzanine. The default mezzanine provides 16 lines, 5-100 V, positive, 3 mA or 9 mA per bias line.
- Can accept a veto signal.