PETsys TOF FEB / D board

PETsys Time-of-Flight Front End Board / D

The PETsys TOF Front End Board D version 2 (FEB/D_V2) (Fig. 1) is part of the PETsys SiPM readout system. The Readout System has three different boards - FEB/D, FEB/A, and DAQ - which together allow assembling a complete and scalable data acquisition system with several tens of thousands SiPM channels for Time Of Flight PET, or similar, applications.
The FEB/D is equipped with a Kintex 7 FPGA. It receives the data from the 16 TOFPET ASICs via the front-end FEB/A boards, and sends the data to the DAQ board in the data acquisition computer. The FEB/D_V2 also receives configuration, clock and sync signals from the DAQ board and distributes them to the ASICs. Optionally, the DAQ board can receive an external veto signal and distribute this veto signal to the FEB/D boards. The FEB/D will ignore all events while the veto signal is on.
Each FEB/D_V2 board measures 104.5x104.5 mm2. Eight FEB/A boards can be connected to one FEB/D board, using either direct board-to-board connectors or using  flexible  at cables. Each FEB/D board collects the data from 1’024 SiPM channels and transmits assembled data frames to the DAQ using an electrical HDMI serial link or using a high-speed op cal link. Several FEB/D boards can be daisy-chained and interfaced to a single DAQ board input. The maximum event rate of the output link (HDMI or op cal) is 72 M events/s.
The FEB/D_V2 can read up to 8 FEB/A boards equipped with TOFPET ASIC2, but with a small adaptor board it will also read FEB/A boards equipped with TOFPET ASIC1.
A mezzanine on the The FEB/D_V2 (middle mezzanine on figure 1) supplies bias voltages to the SiPMs. The default mezzanine provides 64 positive bias voltages in the range 5-100 V, with a maximum current of 550 μA per bias line. A customised mezzanine version, e. g. supplying negative bias voltage, or a larger current, can be developed on request. DC-DC converters and regulators on the FEB/D motherboard provide the low voltages for the ASICs.

 

 

 

   Figure 1: FEB/D_V2 board .

Main Features

  • Reading 1024 independent SiPM channels from 16 TOF ASICs.
  • Equipped with Kintex 7 FPGA.
  • Comptible with TOF ASIC1, TOF ASIC2, and FEB/A and DAQ boards.
  • Data output mezzanine: micro HDMI, and optical
  • Max event output rate (HDMI links or op cal): 72 M events/s
  • Daisy chaining of data output data links allows reading several 10 FEB/Dboards with one DAQ board.
  • External clock and synchroniztion provided by the HDMI cable.
  • Clock frequency 200 MHz.
  • External supply voltage: 12 Vdc.
  • On board DC-DC converters supply power to the ASICs in the FEB/A boards.
  • SiPM bias voltages produced in a mezzanine. The default mezzanineprovides 64 lines, 5-100 V, postive, 550 micro Amp per bias line.
  • Can accept a veto signal.