PETsys TOF PET ASIC

PETsys TOF PET ASIC PDF

1. Overview

1.1. Features:

• Low power, low noise SiPM readout ASIC for Time of Flight applications
• Integrates signal conditioning and discrimination circuitry and high-performance TDCs for each of 64 independent channels
• 25 ps r.m.s. intrinsic time resolution
• Charge measurement with time-over-threshold
• Dynamic range: 300 pC
• SNR (Qin = 100 fC): 25 dB
• Amplifier noise (in total jitter): 25 ps for 1 p.e. signal
• TDC time binning: 50 ps (option 25 ps)
• Coarse Gain: G0, G0/2, G0/4
• Max Channel Hit rate: 160 kHz
• Channel masking: programmable
• SiPM HV fine biasing: range 500 mV

• SiPM family supported: positive or negative signal polarity (terminal capacitance up to 320 pF guarantees noise, SNR and intrinsic time resolution as above stated)
• On-chip Calibration Circuitry: internal pulse generator, programmable 6-bit amplitude
• Max Output Data Rate: 320 Mb/s (640 Mb/s with double-data-rate)
• Fully digital output, 2 data links DDR compatible
• All-LVDS digital interface
• Operation frequency 80-160 MHz
• Available in a 128 System-in-a-Package (BGA 17x17 mm)
• AV DD = 1.5V
• DV DD_core = 1.5V
• DV DD_IO = 2.5V
• Power per Channel: 8-11 mW

1.2. Description

The TOFPET ASIC is made up of 64 channels, bias and calibration blocks and a global controller.
One edge is free of pins, such that a rotated twin chip can be abutted to build a compact 128 channel module (Configuration shown in fig. 1). Nominal operation mode uses a 160 MHz CLK_IN clock generated off-chip. Up to two LVDS data output links (TX0, TX1) are available (SDR or DDR), for a total bandwidth from 160 to 640 Mbit/s. An output clock for synchronous transmission is available, while a TX training mode can also be used to avoid the need for CLK_OUT. Data is output in 6.4 μs frames, with up to 48 events per frame. A 10 MHz (SCLK) SPI configuration interface writes (SDI) and reads (SDO) the channel configuration, controls calibration procedures and test modes. The configuration is enabled by setting the chip select pin CS high.
When in test mode, the chip can produce a test pulse at the input of any TDC or the front-end of each channel. Several channels can be tested simultanesously. The test strobe can be either internally generated, via a SPI command, or fed externally from the Test_Pulse pin - the latter can be disabled by a global setting. Depending on the channel configuration setting, the channel will either:

• Ignore it
• Generate a test pulse at the front end
• Generate a test pulse for the TDCs (selectable phase with respect to the clock, used also for calibration and non-linearity correction)
• Generate synchronous calibration pulses for the TDCs (1 or 3 clock charge)

Figure 1
The 128-channel SiP assembly of two TOFPET ASICs.

SYNC_RST is a dual purpose reset: A single clock active high strobe causes everything BUT the configuration registers to be reset. A two or more clock strobe causes the entire ASIC to be reset.
The clock, reset and coarse time vector is internally propagated by the global controller to each channel, along with the configuration settings.

The channel analogue very-front-end is represented in Fig. 2. The very front-end of the analogue chain comprises a low-impedance input stage that conveys the photodetector current signal into a high output impedance node. Two replicae of the signal are amplified by a trimmable gain (2.5 − 0.7 kΩ) transimpedance amplifier. Each channel comprises a set of two branches for independent processing of the rising and falling edge of the signal. The fast rising edge (Vout_T) of the pulse is discriminated at a very low threshold for timing purposes (DOT_int (Timing Trigger)). The falling edge (Vout_E) generates a second trigger (at a higher threshold) that will be used for charge measurement (DOE_int (Energy Trigger)). Figure 2: Simplified representation of the front-end amplifier chain. The specific case of a anode-type readout is shown

The DOT int and DOE int time stamps are obtained with a dual mixed-mode TDC. This block comprises two analogue TDCs based on time interpolation and a digital control block that manages the analogue circuitry operation and the data/configuration links with the global controller.
For each event of interest, a TAC (time-to-analogue converter) records a voltage which is proportional to the phase between the time of the trigger and a known phase of the clock. This voltage is then coverted with an Wilkinson ADC, and an appropriate choice of capacitance values and charge/discharge current values yields a time interpolation factor of 128. The inherent low-rate capability of this kind of circuit is overcome by a multi-buffer design that derandomizes the time of arrival of each event. At the nominal frequency of 160 MHz, the measured time interval is digitized with 50 ps binning (optionally 25 ps), which is associated to a 10-bit coarse time stamp, provided by a top clock counter. The data set produced by a valid event consists of an identification field (channel and TAC IDs) and a set of 5 10-bit time stamps.

• Time stamp of DOT_int
  • tcoarse: value of the global coarse counter when the Timing trigger is recorded
  • SoC: value of the global coarse counter when the Timing TDC starts the conversion
  • tEoC: value of the global coarse counter when the Timing TDC ends the conversion
• Time stamp of DOE_int
  • ecoarse: value of the global coarse counter when the Energy trigger is recorded
  • SoC: (The conversion starts at the same time in both TDCs, so only one SoC value is stored.)
  • eEoC: value of the global coarse counter when the Energy TDC ends the conversion

2. Chip Operation

This section describes the operation modes of the chip. Refer to the TOFPETv1 User Guide for a thorough description of the configuration procedure.

2.1. Hit Validation Schemes

Two configuration bits, sync and praedictio define the operation mode of the TDCs.
If (sync == 1, praedictio == 0), the latched and synchronous versions of time (DOTL) and energy (DOEL) triggers are polled every clock (acceptance gate up to 1 clock cycle). This is a conservative approach based on synchronous polling of both triggers, but has an acceptance of the energy trigger that is a function of the chip clock. Such feature can become a concern for systems running at lower clock frequency or with very high dark pulse rates, because it can generate valid data with a time trigger associated with a dark pulse immediately preceding an energy event. To overcome this, a configurable gate (t_DOE−t_DOT ) can be generated by analogue circuitry, which will issue external falsehit and validhit flags.
This operation mode (sync == 0, praedictio == 0) overrides the synchronous operation and creates an acceptance window (time elapsed between the first low-threshold trigger and the higher threshold event validation) that is not locked to the clock frequency and can be reduced down to 1.5 ns. A trigger error flag is issued when a dark count precedes a true event in the defined time window. The acceptance gate is set by cgate_cfg2, cgate_cfg1 and cgate_cfg0, in an interval between 1.5 ns and 9 ns. If the energy trigger goes high while the gate is open, a validhit strobe is generated. Once this gate is shut, bits latch_cfg2, latch_cfg1 and latch_cfg0 set the delay after which a falsehit flag is issued if the energy trigger is low - the default value is 2 ns.
Working on sync/async modes, the dark pulse rate is saved into an internal counter, where the counter value increases each time the time trigger is issued but the energy threshold is not reached.
Each one of the two above configurations imply that the TDC control logic identifies each single-photon trigger, tags it as a spurious event if the energy validation fails, issues a reset to the written buffer and assigns a new one.
A third operation mode (sync == 1, praedictio == 1), a delayed version of the DOT is masked unless there is an energy trigger.
This is the default mode - limited logic switching and noise injected into the analogue substrate due to TAC re-assignment. For very low event rate (below 1 kHz), TAC Refresh may need to be enabled to preserve the timing performance - refer to the document TOFPETv1 User Guide. If the charge collection per channel is low (case of a monolithic crystal module), the energy threshold must be set very low (2-4 pe above V_{th_T}).

3. ASIC data link

The ASIC’s data output consists of 2 serial LVDS links, operating at clock frequency (80 - 160 MHz), which can operate at single or double data rate (SDR or DDR).
The ASIC will support both source synchronous and ”calibrated” reception schemes. For the first, the ASIC will also transmit a source synchronous clock. For the second, the ASIC supports a training mode in which the links transmit a ”0101” pattern.
Data is distributed across active links in octets; each link in individually 8B/10B encoded and special control codes are used to delimit frames:

• K28.1 transmitted before the frame
• K28.5 transmitted after the frame, and used as filler

4. ASIC control link

The ASIC’s control link is SPI-like and consists of 4 lines:

• CS (chip select)
• SCLK (serial clock, 10 MHz)
• SDI (serial data in)
• SDO (serial data out)

• The SCLK clock may be disabled, but must be active one clock before CS is asserted until one clock after CS is de-asserted.
• CS must be asserted during all the communication process.
• The SDO line cannot be shared with other chips, as the IO does not remain in high-impedance if unused.
• The commands to the ASIC follow a general structure
  • 4 bit command
  • 7 bit channel address (if applicable)
  • N1 bit long command data (if applicable)
  • 8 bit CRC
• After the command has been sent, the ASIC will set SDO to 1 if the command was successfully acknowledged, 0 else. If the command is not validated, the ASIC will not take any internal action.
• Write commands require that CS and SCLK to be kept active for an extra N₂ clock cycles, while the ASIC’s internal machinery works.
• In case of read commands, data will be written after the acknowledgment cycle.
• Read data will also be followed by a CRC8.
• All fields are transmitted MSB first.
• The 8 bit CRC’s polynomial is x8 + x2 + x + 1 (CCITT CRC) with an initial value of 0x8A.

4.1. Test Pulse

This command is used to internally broadcast a test pulse to the channels. It generates K + 1 pulses, each with M+1 clocks in length and separated by 128*(N +1) clocks. The channel’s CHn TEST PULSE net is multiplexed and broadcasts this internally generated pulse only if the External Pulse Enable global configuration bit is off. Otherwise (cf. section 5) the net is driven by the external TP.

4.2. Dark Counter

For SiPM characterization, a dark count meter is available. Each channel has an embedded 10-bit counter, incremented each time a signal triggers the DOT but not DOE. This feature works only when the chip is in Synchronous Mode (sync==1, praedictio==0), as described in section 2.1.
The counter continuously counts over a set interval, stores that value and then resets itself to zero. The last stored value can be read via the SPI interface. The counting interval is configurable in exponential steps: 2¹⁰, 2¹¹, 2¹², to 2²⁵ clocks (6.4 μs to 209 ms).
When Count Trigger Error==1, and if the chip is Asynchronous Mode (sync==0, praedictio== 0), the counter counts trigger errors instead of dark counts. A trigger error is a condition when the channel has processed a valid hit (DOE was triggered), but had a preceeding dark count too close in time. In this situation, the event would be seen as valid but the time stamp being that of the dark count - an error condition is generated.
Both configurations are global.

5. Pin Configuration

The pin assignment and pad topology is depicted in Table 1.

PETsys TOF PET ASIC PDF