PETsys TOF Front End Board / D

PETsys TOF Front End Board / D PDF

The PETsys TOF Front End Board type D (FEB/D) is a carrier of FEB/A readout boards for Time Of Flight applications (Fig. 1). Up to eight FEB/A boards (Fig. 2) can be connected to the FEB/D, using either direct board-to-board connectors or flexible kapton cables.

The FEB/D is optimised for being used together with arrays of LYSO scintillating crystals associated to SiPMs and eight FEB/A boards as a building block for high resolution PET scanners using the Time Of Flight information. Each FEB/D board measures 118.0x118.0 mm and is four-side buttable such as to form a continuously sensitive area with almost no dead space.

The FEB/D boards can be integrated with the PETsys DAQ board forming a complete scalable data acquisition system with several ten thousand channels. Each FEB/D board collects the data of 1024 channels and transmits assembled data frames through a high-speed serial link (1.6 Gbps). The data links of several FEB/D boards can be daisy-chained and interfaced to a single DAQ board to create a compact data acquisition system. The maximum output event rate per FEB/D is 16 M event/s (full event format) or 32 M events/s (compact event format).

The FEB/D board is supplied with 24 V. On board DC-DC converters and regulators provide the required low voltages as well as 64 configurable SiPM bias voltage lines.

The TOF ASIC (Fig. 3) used in PETsys frontend system is optimized for timing and has 25 ps time resolution (r.m.s.). It uses a low threshold for timing and a high threshold for accepting the event. Both thresholds are separately configurable for each channel. Every time one of the 64 channels exceeds the high threshold a record is created giving the channel number, the time and the amplitude of the event. Activity in one channel does not cause any dead-time on one of the other channels.

Figure 2
Drawing of the FEB/A board(top and bottom).

I/O connectors:

Each of the eight FEB/A connectors has two rows of pins, separated by ground, one row assigned to the bias voltages and the low voltages, and the other row assigned to the digital signals. The connector is of type SAMTEC_QTH-030-0H-L-D-A on the FEB/D side matching a connector of type SAMTEC_QSH-030-01-L-D-A on the FEB/A side.
The lines in the FEB/A connector include:

• CLK_IN: Nominal operation mode uses a 160 MHz clock
• SPI interface: 10 MHz configuration interface writes and reads the configuration
• SYNC RST: dual purpose reset (full and partial reset)
• BIAS V: 8 bias voltages lines
• TX_OUT (0-3): 4 LVDS data links
• TEMP: temperature sensor
• Supply voltages: 1.5 V (analog), 1.2 V (digital), 2.5 V (I/O).

The FEB/D board has a mini HDMI connector carrying the output data link, the input configuration link, as well as the clock and synchronization lines. All signals are LVDS.

Data frames:

The ASICs transmits data in frames (Fig.4), each frame consisting of the events captured in a 1024 clock period (6.4 μs frames). The FEB/D FPGA receives 16 ASIC point-to-point data links, builds data frames with all events and outputs the data through a high-speed LVDS serial link. The output link is 8B/10B encoded and a CRC is added at the end of the frame.

Figure 3
The 128-channel assembly of two TOF ASICs.

Figure 4
Data frame format (full event data). Each event includes time counters and channel ID (6-bit tag of the channel that generates the data). A 2-bit TAC ID records the index of the TAC used for a particular event.

PETsys TOF Front End Board / D PDF